Programmable controller

Provided is a programmable controller with which pipeline processing interrupts arising from read-modify-write operations, which occur frequently in programmable controllers comprising ladder language bit operation processors, are avoided. A pipeline stage (execution stage (EX)) which carries out bi...

Full description

Saved in:
Bibliographic Details
Main Authors NAKAMIKAWA TETSUAKI, YAMADA TSUTOMU, KAMIWAKI TADASHI, SHIRAISHI MASAHIRO, OTANI TATSUYUKI
Format Patent
LanguageChinese
English
Published 21.08.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Provided is a programmable controller with which pipeline processing interrupts arising from read-modify-write operations, which occur frequently in programmable controllers comprising ladder language bit operation processors, are avoided. A pipeline stage (execution stage (EX)) which carries out bit operations and bit data merges is disposed after a pipeline stage (read stage (R)) which loads data subject to read-modify-write in a buffer register (141) and retains the address of the subject data in an address retention circuit (22), and thereafter, a pipeline stage (write stage (W)) which stores the merge result at the address that is retained at the read stage (R) is disposed.
Bibliography:Application Number: CN201180059507