Static random access memory (SRAM) write assist circuit with leakage suppression and level control

A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of...

Full description

Saved in:
Bibliographic Details
Main Authors RAMADURAI VINOD, PILO HAROLD, ARSOVSKI IGOR
Format Patent
LanguageEnglish
Published 08.07.2015
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages.
Bibliography:Application Number: CN201180057492