High-speed and low-power-consumption CMOS full adder and operation method thereof

• Main Authors: JIA SONG, ZHANG GANGGANG, LV SHIGONG, WANG YUAN, LIU LI
• Format: Patent
• Language: Chinese; English
• Published: 31.07.2013
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

The invention discloses a high-speed and low-power-consumption CMOS (Complementary Metal Oxide Semiconductor) full adder and an operation method thereof. The full adder comprises an exclusive-or and exclusive-nor generation circuit, a carry output circuit and a basic unit summation circuit, wherein the exclusive-or and exclusive-nor generation circuit is used for generating an intermediate signal; an exclusive-or signal P, an exclusive-nor signal, the exclusive-or and exclusive-nor generation circuit and the carry output circuit generate a carry output signal together; and the exclusive-or and exclusive-nor generation circuit, the carry output circuit and the basic unit summation circuit generate a basic unit summation output signal of the CMOS full adder together. According to the full adder, good drive capability and good robustness of the traditional CMOS full adder are ensured, intermediate nodes and capacitors of the full adder are decreased; a load of an input signal is reduced; the quantity of used tra