Multistage collector for outputs in multiprocessor systems

The invention relates to a multistage collector for outputs in a multiprocessor systems. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream be...

Full description

Saved in:
Bibliographic Details
Main Authors MCCOMBE JAMES A, CLOHSET STEVEN JOHN, REDGRAVE JASON RUPERT, PETERSON LUKE TILMAN
Format Patent
LanguageChinese
English
Published 10.07.2013
Subjects
CALCULATING
COMPUTING
COUNTING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:The invention relates to a multistage collector for outputs in a multiprocessor systems. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.
Bibliography:Application Number: CN201210350398