Thin film transistor array fabrication method, thin film transistor array, and display device
This thin film transistor array fabrication method includes the following: a third step wherein a gate insulating layer (13) is formed on top of a plurality of gate electrodes (12); a fourth step wherein an amorphous silicon layer (14) is formed on top of the gate insulating layer (13); a fifth step...
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Main Author | |
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Format | Patent |
Language | Chinese English |
Published |
15.05.2013
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Subjects | |
Online Access | Get full text |
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Summary: | This thin film transistor array fabrication method includes the following: a third step wherein a gate insulating layer (13) is formed on top of a plurality of gate electrodes (12); a fourth step wherein an amorphous silicon layer (14) is formed on top of the gate insulating layer (13); a fifth step wherein the amorphous silicon layer (14) is crystallized to produce a crystalline silicon layer (15); and a sixth step wherein source electrodes and drain electrodes (18) are formed. In the third step, the film thickness of the gate insulating layer (13) on top of the plurality of gate electrodes (12) is formed in a film thickness range wherein the light absorption rate of laser light of the amorphous silicon layer (14) on top of the gate electrodes (12) has a positive correlation to an oxide film thickness equivalent to the gate insulating layer (13), and in the fourth step the film thickness of the amorphous silicon layer (14) on top of the plurality of gate electrodes (12) is formed in a film thickness range wh |
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Bibliography: | Application Number: CN201180004138 |