Method for decreasing series resistors of P type substrate hetero junction with intrinsic thin layer (HIT) solar cell

• Main Authors: SHI JIANHUA, LIU ZHENGXIN, CUI YANFENG, MENG FANYING, YUAN SHENGZHAO, LU ZHONGDAN
• Format: Patent
• Language: Chinese; English
• Published: 08.05.2013
• Subjects: BASIC ELECTRIC ELEMENTS; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGYGENERATION, TRANSMISSION OR DISTRIBUTION; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

The invention discloses a method for decreasing series resistors of a P type substrate hetero junction with intrinsic thin layer (HIT) solar cell. The P type HIT solar cell comprises a P type crystalline silicon substrate layer, a first intrinsic non-crystalline silicon layer, a second intrinsic non-crystalline silicon layer, a N type non-crystalline silicon layer, a P type non-crystalline silicon layer, a first transparent conductive oxide (TCO ) layer and an electrode, a second TCO layer and an electrode. The first intrinsic non-crystalline layer and the second intrinsic non-crystalline layer are arranged on two sides of the P type crystalline silicon substrate layer, the N type non-crystalline layer is arranged on the outer side of the first intrinsic non-crystalline silicon layer, the P type non-crystalline silicon layer is arranged on the outer side of the second intrinsic non-crystalline silicon layer, the first TCO layer and the electrode are arranged on the outer side of the N type non-crystalline sil