Bit synchronization correction method for multilevel parallel analog-digital converter
The invention discloses a bit synchronization correction method for a multilevel parallel analog-digital converter. The method includes the steps of connecting differential output of a folding circuit to comparators to generate a synchronization correction signal determining correction range; and su...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | Chinese English |
Published |
06.03.2013
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | The invention discloses a bit synchronization correction method for a multilevel parallel analog-digital converter. The method includes the steps of connecting differential output of a folding circuit to comparators to generate a synchronization correction signal determining correction range; and subjecting output of a coarse conversion module to n-bit synchronization correction according to output of a fine conversion module and the synchronization correction signal. The method is simple in logic, the correction range is definable, error correction and bit synchronization can be achieved in wide range, the number of the comparators is decreased, and power consumption is lowered. |
---|---|
AbstractList | The invention discloses a bit synchronization correction method for a multilevel parallel analog-digital converter. The method includes the steps of connecting differential output of a folding circuit to comparators to generate a synchronization correction signal determining correction range; and subjecting output of a coarse conversion module to n-bit synchronization correction according to output of a fine conversion module and the synchronization correction signal. The method is simple in logic, the correction range is definable, error correction and bit synchronization can be achieved in wide range, the number of the comparators is decreased, and power consumption is lowered. |
Author | LIU ZHEN XU SHUMIN GUO BAOAN |
Author_xml | – fullname: GUO BAOAN – fullname: XU SHUMIN – fullname: LIU ZHEN |
BookMark | eNqNi7sKwkAQAK_Qwtc_nB8Q0KgESw2KlZXYynLZJAeb3bBZA_r1BvEDrGaKmakbsTBO3P0YzXcvDrUKxzdYFPZBVDF8tUGrpfClqG-eZJGwR_ItKBANAgwkVVLEKhrQMHKPaqhzNy6BOlz8OHPL8-mWXxJs5YFdCwEZ7ZFf16t0v8u2aXbY_NN8APC1PHs |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
ExternalDocumentID | CN102957427A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_CN102957427A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 12:12:08 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | Chinese English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_CN102957427A3 |
Notes | Application Number: CN20111238021 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130306&DB=EPODOC&CC=CN&NR=102957427A |
ParticipantIDs | epo_espacenet_CN102957427A |
PublicationCentury | 2000 |
PublicationDate | 20130306 |
PublicationDateYYYYMMDD | 2013-03-06 |
PublicationDate_xml | – month: 03 year: 2013 text: 20130306 day: 06 |
PublicationDecade | 2010 |
PublicationYear | 2013 |
RelatedCompanies | AISINO CORPORATION INC |
RelatedCompanies_xml | – name: AISINO CORPORATION INC |
Score | 2.9925163 |
Snippet | The invention discloses a bit synchronization correction method for a multilevel parallel analog-digital converter. The method includes the steps of connecting... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY |
Title | Bit synchronization correction method for multilevel parallel analog-digital converter |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130306&DB=EPODOC&locale=&CC=CN&NR=102957427A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1dS8MwFL3MKeqbTkXnBxGkb8Xa7z4UsenKENYNmWNvo23aWSndsBXRX-9N1jlf9C0kEJLATU6Sc-4BuNEiBBmMmTJC_0zWLTuWI0WLZSe-Y2riKDazuRp5EJr9Z_1xakxb8LrWwog8oR8iOSJGVILxXov9erl5xPIFt7K6jXOsWtwHY9eXmtsx35AVU_I9tzca-kMqUerSUAqfEOuqjoHXQOthC7YRRls8GnoTj6tSlr-PlOAAdkbYW1kfQuvrpQN7dO281oHdQfPhjcUm9qojmHh5TarPMhHpbFfqSZJwcw0hTSArL2iCIJQIlmDB6UCEp_YuCixEJX-mkVk-5zYhRLDNOZ3zGK6D3pj2ZRzg7Gc1ZjTczEU7gXa5KNNTIA7LHN2wMzO1FD0zWZSomWPrWcpMLYl16wy6f_fT_a_xHPZV4QHBbSAuoF2_vaeXeBLX8ZVYwm-JHZAP |
link.rule.ids | 230,309,783,888,25576,76876 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1dS8MwFL3MKc43ncqcXxGkb8Xa7z4McenG1LUbMsfeStu0WhndcBXRX-9N1jlf9C0kEJLATU6Sc-4BuNRCBBmMmTJC_1TWLTuSQ0WLZCe6ZmrsKDazuRrZ883ek34_MSYVeF1pYUSe0A-RHBEjKsZ4L8R-PV8_YrmCW7m4ijKsmt10Ry1XKm_HfENWTMlttzrDgTugEqUt6kv-I2Jd1THwGmjdbsAmQmyLR0Nn3OaqlPnvI6W7C1tD7C0v9qDy9VKHGl05r9Vh2ys_vLFYxt5iH8btrCCLzzwW6WyX6kkSc3MNIU0gSy9ogiCUCJbglNOBCE_tPZ1iIcz5M43MsmduE0IE25zTOQ_gotsZ0Z6MAwx-ViOg_nou2iFU81meNIA4LHV0w07NxFL01GRhrKaOracJM7U40q0jaP7dT_O_xnOo9UZeP-jf-Q_HsKMKPwhuCXEC1eLtPTnFU7mIzsRyfgN3L5MC |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Bit+synchronization+correction+method+for+multilevel+parallel+analog-digital+converter&rft.inventor=GUO+BAOAN&rft.inventor=XU+SHUMIN&rft.inventor=LIU+ZHEN&rft.date=2013-03-06&rft.externalDBID=A&rft.externalDocID=CN102957427A |