Bit synchronization correction method for multilevel parallel analog-digital converter

The invention discloses a bit synchronization correction method for a multilevel parallel analog-digital converter. The method includes the steps of connecting differential output of a folding circuit to comparators to generate a synchronization correction signal determining correction range; and su...

Full description

Saved in:
Bibliographic Details
Main Authors GUO BAOAN, XU SHUMIN, LIU ZHEN
Format Patent
LanguageChinese
English
Published 06.03.2013
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
Online AccessGet full text

Cover

More Information
Summary:The invention discloses a bit synchronization correction method for a multilevel parallel analog-digital converter. The method includes the steps of connecting differential output of a folding circuit to comparators to generate a synchronization correction signal determining correction range; and subjecting output of a coarse conversion module to n-bit synchronization correction according to output of a fine conversion module and the synchronization correction signal. The method is simple in logic, the correction range is definable, error correction and bit synchronization can be achieved in wide range, the number of the comparators is decreased, and power consumption is lowered.
Bibliography:Application Number: CN20111238021