Method for improving KINK defect in dual damascene process

• Main Authors: GAI CHENGUANG, HUANG JUN, ZHANG YU
• Format: Patent
• Language: Chinese; English
• Published: 16.01.2013
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to the field of semiconductor manufacture, in particular to a method for improving a KINK defect in a dual damascene process. According to the method for improving the KINK defect in the dual damascene process, a low-K dielectric layer is arranged between a metal hard mask layer and an ultra-low K dielectric layer, and a K-value progressive structure of which dielectric layers with different K values (low-K dielectric layers and ultra-low K dielectric layers) reflect different etch rates during plasma etching is used for fulfilling the aim of protecting a sidewall, so that the critical dimension (CD) of the bottom of a semiconductor device is kept, and the specific defects of kink, bowing or the like of the sidewall are also improved to further facilitate a subsequent barrier and Cu filling process, reduce filling and grinding defects and improve the yield of the product.