High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex

• Main Authors: ZHENG JINYAN, LIU WEI, TIAN BIAO, LIU JUN, LI LIHUA, BI WENJING, YANG NAN, PENG MING, WANG DONG, RONG GAOFENG, ZHAO JING, ZHANG QING, ZHANG GUOYU, CHEN PENG
• Format: Patent
• Language: Chinese; English
• Published: 02.01.2013
• Subjects: CONTROL OR REGULATING SYSTEMS IN GENERAL; CONTROLLING; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS; PHYSICS; REGULATING

The invention belongs to the field of testing technology of programmable logic element and particularly relates to a high data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex, and aims to solve the problem that the high data volume FPGA simulating test is insufficient in internal memory and improves the sufficiency of the high data volume FPGA simulating test. The high data volume FPGA simulating testing method comprises the step of reducing the internal memory source used for the simulating test within the allowable capacity range of a simulating tool, dividing the RAM (Random Access Memory) data to be tested into a plurality of parts based on the volume of the internal memory source, testing the plurality of divided RAM data through a time sharing multiplex way, and dynamically calculating the internal memory space of a system as current simulating requirement through an internal memory dynamic managing method, and distributing and releasing the internal