Address delay circuit of semiconductor memory apparatus

• Main Author: JAE BUM KO
• Format: Patent
• Language: Chinese; English
• Published: 26.09.2012
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

The invention provides an address delay circuit of a semiconductor memory apparatus, including a first group control pulse generation unit configured to generate a first control pulse after input of a first group column address strobe pulse and passage of a time corresponding to a first set multiple of one cycle of a clock, a second group control pulse generation unit configured to generate a second control pulse after input of a second group column strobe address pulse and passage of a time corresponding to a second set multiple of the one cycle of the clock, a first address storage unit configured to receive and store a first group external address in response to the first control pulse, and output a first group internal address, and a second address storage unit configured to receive and store a second group external address in response to the second control pulse, and output a second group internal address.