Method of erasing a flash eeprom memory
A method for erasing a flash EEPROM memory device is disclosed. The method includes: a first voltage bias of positive polarity applied across a well electrode and a second semiconductor region during -F/N channel through a tube and a second voltage bias of negative polarity applied across a control...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | Chinese English |
Published |
18.07.2012
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A method for erasing a flash EEPROM memory device is disclosed. The method includes: a first voltage bias of positive polarity applied across a well electrode and a second semiconductor region during -F/N channel through a tube and a second voltage bias of negative polarity applied across a control grid electrode; a third voltage bias of positive polarity applied across a well electrode and a second semiconductor region during disfigurement reduces after period of -F/N channel tunneling and a first zero voltage bias of positive polarity applied across the control grid electrode; a fourth voltage bias of negative polarity applied across the control grid electrode during disfigurement auxiliary tunneling after disfigurement reduces and a second zero voltage bias applied across a well electrode and a second semiconductor region. |
---|---|
Bibliography: | Application Number: CN201210010287 |