Signal event upset resistance D trigger capable of being set and reset

• Main Authors: LI PENG, LIANG BIN, CHI YAQING, CHEN JIANJUN, HE YIBAI, LIU BIWEI, LI ZHENTAO, LIU ZHEN, DU YANKANG
• Format: Patent
• Language: Chinese; English
• Published: 28.03.2012
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

The invention discloses a signal event upset resistance D trigger capable of being set and reset, and is aimed at raising signal event upset resistance capability of the signal event upset resistance D trigger capable of being set and reset. The trigger comprises a clock circuit, a reset buffer circuit, a main latch register, a secondary latch register and an output buffer circuit. The main latch register is composed of 14 PMOS tubes and 14 NMOS tubes. The secondary latch register is composed of 10 PMOS tubes and 10 NMOS tubes. Both the main latch register and the secondary latch register are subjected to duplication redundancy reinforcement, and a C2MOS circuit in the main latch register is improved, i.e., a pull-up PMOS tube and a pull-down tube which are mutually redundant in the C2MOS circuit are separated. The trigger in the invention has strong signal event upset resistance capability, is suitable for a standard cell of a signal event upset resistance reinforcement integrated circuit, and is applied to