Single event upset resistant settable and resettable scan structure D flip-flop

• Main Authors: LI PENG, LIANG BIN, LIU ZONGLIN, CHI YAQING, HU CHUNMEI, CHEN JIANJUN, HE YIBAI, LIU BIWEI, QIN JUNRUI, DU YANKANG
• Format: Patent
• Language: Chinese; English
• Published: 28.03.2012
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

The invention discloses a single event upset resistant settable and resettable scan structure D flip-flop, aiming at improving the single event upset resistance of the single event upset resistant settable and resettable scan structure D flip-flop. The scan structure D flip-flop is composed of a clock circuit, a scanning control buffer circuit, a resetting buffer circuit, a master latch, a slave latch and an output buffer circuit, wherein the master latch is composed of 20 PMOS (P-channel Metal Oxide Semiconductor) FETs (Field Effect Transistors) and 20 NMOS (N-channel Metal Oxide Semiconductor) FETs, the slave latch is composed of 10 PMOS FETs and 10 NMOS FETs, duplication redundant reinforcement is performed on both the master latch and the slave latch, and the C2MOS (Clocked Complementary Metal Oxide Semiconductor) circuit structures in the master latch and the slave latch are improved, i.e. a pull-up circuit and a pull-down circuit in the mutually redundant C2MOS circuits are separated. The scan structure