Single-event-upset resistant scan structure D trigger capable of being reset synchronously
The invention discloses a single-event-upset resistant scan structure D trigger capable of being reset synchronously, and aims to improve the single-event-upset resistance of the single-event-upset resistant scan structure D trigger capable of being reset synchronously. The single-event-upset resist...
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Main Authors | , , , , , , , , |
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Format | Patent |
Language | Chinese English |
Published |
22.02.2012
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Subjects | |
Online Access | Get full text |
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Abstract | The invention discloses a single-event-upset resistant scan structure D trigger capable of being reset synchronously, and aims to improve the single-event-upset resistance of the single-event-upset resistant scan structure D trigger capable of being reset synchronously. The single-event-upset resistant scan structure D trigger capable of being reset synchronously consists of a clock circuit, a scanning control buffer circuit, a master latch, a slave latch, a first phase inverter circuit and a second phase inverter circuit, wherein the master latch consists of eighteen P-type metal-oxide semiconductor (PMOS) tubes and eighteen N-type metal-oxide semiconductor (NMOS) tubes; the slave latch consists of ten PMOS tubes and ten NMOS tubes; and both the master latch and the slave latch are subjected to duplication redundancy reinforcement, and clocked complementary metal-oxide semiconductor (C MOS) circuit structures in the master latch and the slave latch are improved, namely pull-up circuits and pull-down circuits |
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AbstractList | The invention discloses a single-event-upset resistant scan structure D trigger capable of being reset synchronously, and aims to improve the single-event-upset resistance of the single-event-upset resistant scan structure D trigger capable of being reset synchronously. The single-event-upset resistant scan structure D trigger capable of being reset synchronously consists of a clock circuit, a scanning control buffer circuit, a master latch, a slave latch, a first phase inverter circuit and a second phase inverter circuit, wherein the master latch consists of eighteen P-type metal-oxide semiconductor (PMOS) tubes and eighteen N-type metal-oxide semiconductor (NMOS) tubes; the slave latch consists of ten PMOS tubes and ten NMOS tubes; and both the master latch and the slave latch are subjected to duplication redundancy reinforcement, and clocked complementary metal-oxide semiconductor (C MOS) circuit structures in the master latch and the slave latch are improved, namely pull-up circuits and pull-down circuits |
Author | HE YIBAI QIN JUNRUI LI PENG DU YANKANG LIU XIANGYUAN CHEN JIANJUN LIANG BIN CHI YAQING SUN YONGJIE |
Author_xml | – fullname: LI PENG – fullname: LIU XIANGYUAN – fullname: LIANG BIN – fullname: CHI YAQING – fullname: CHEN JIANJUN – fullname: HE YIBAI – fullname: QIN JUNRUI – fullname: SUN YONGJIE – fullname: DU YANKANG |
BookMark | eNqNjL0KwkAQBlNo4d87rA8QMCbYS1SsbLSyCZfjSwwce8ftnpC3N4IPYDXNzCyzGXvGInveB-4dcrzBmqcgUIqQQdSwkljDJBqT1RRBJ9I49D0iWRNM60C-oxbT4dtMpYxsX9GzT-LGdTbvjBNsflxl28v5UV9zBN9AgrFgaFPfit2-PBRVtTuW_zgfs2s9WA |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
ExternalDocumentID | CN102361440A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_CN102361440A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 12:11:01 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | Chinese English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_CN102361440A3 |
Notes | Application Number: CN20111322679 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120222&DB=EPODOC&CC=CN&NR=102361440A |
ParticipantIDs | epo_espacenet_CN102361440A |
PublicationCentury | 2000 |
PublicationDate | 20120222 |
PublicationDateYYYYMMDD | 2012-02-22 |
PublicationDate_xml | – month: 02 year: 2012 text: 20120222 day: 22 |
PublicationDecade | 2010 |
PublicationYear | 2012 |
RelatedCompanies | NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY, PLA |
RelatedCompanies_xml | – name: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY, PLA |
Score | 2.949467 |
Snippet | The invention discloses a single-event-upset resistant scan structure D trigger capable of being reset synchronously, and aims to improve the... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
Title | Single-event-upset resistant scan structure D trigger capable of being reset synchronously |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120222&DB=EPODOC&locale=&CC=CN&NR=102361440A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFD7MKeqbTkXnhQjSt-DW2-hDEZduDGHd0CnDl9GkqRdKV9YOmb_ek7g5X_QtJOSQHPhy8iU5XwCuXI9HIkYgScsR1G5ZNuU8smgzcoTjma609avKfuj2Hu27sTOuwPsqF0brhH5ocURElEC8l3q9zteHWIF-W1lc8zesmt50R35gLNlx01T8xQjafmc4CAbMYMxnoRHe-0qhQHGfxu0GbKpttNLZ7zy1VVZK_jukdPdga4jWsnIfKp-vNdhhq5_XarDdX154Y3GJveIAnh8wyqSSasklOs8LWRLkymr_l5WkQBeRbzHY-UySgJRIu1_kjAiMhjyVZJoQLtGC6oM9i0UmlC4uEv90cQiX3c6I9SgOcvLjkQkL1_OxjqCaTTN5DKTV4AinJGp4ifqGyvJ4LDzXMWOpdALj5ATqf9up_9d4CrvKuzqX2zyDKk5HnmM0LvmFduMXPFyQKw |
link.rule.ids | 230,309,786,891,25594,76906 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bT8IwFD5BNOKbokbxVhOzt0XYNXtYjHQQVBhE0RBfyNp1XkIGYSMGf72nFcQXfWva9KQ9ydfTr-35CnDheCziMQJJmDbXLde0dMYiU69FNrc9wxGWelXZCZ3Wo3U7sAcFeF_mwiid0A8ljoiI4oj3XK3Xk9UhVqDeVmaX7A2rxlfNvh9oC3ZcMyR_0YK63-h1gy7VKPVpqIX3vlQokNyner0G665U55Vbp6e6zEqZ_A4pzW3Y6KG1NN-BwudrGUp0-fNaGTY7iwtvLC6wl-3C8wNGmZHQleSSPptkIifIleX-L81Jhi4i32Kws6kgAcmRdr-IKeEYDdlIkHFCmEALsg_2zOYpl7q4SPxH8z04bzb6tKXjIIc_HhnScDUfcx-K6TgVB0DcKkM4JVHVS-Q3VKbHYu45thELqRMYJ4dQ-dtO5b_GMyi1-p32sH0T3h3BlvS0yus2jqGIUxMnGJlzdqpc-gUj75MY |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Single-event-upset+resistant+scan+structure+D+trigger+capable+of+being+reset+synchronously&rft.inventor=LI+PENG&rft.inventor=LIU+XIANGYUAN&rft.inventor=LIANG+BIN&rft.inventor=CHI+YAQING&rft.inventor=CHEN+JIANJUN&rft.inventor=HE+YIBAI&rft.inventor=QIN+JUNRUI&rft.inventor=SUN+YONGJIE&rft.inventor=DU+YANKANG&rft.date=2012-02-22&rft.externalDBID=A&rft.externalDocID=CN102361440A |