Single-event-upset resistant scan structure D trigger capable of being reset synchronously

• Main Authors: LI PENG, LIU XIANGYUAN, LIANG BIN, CHI YAQING, CHEN JIANJUN, HE YIBAI, QIN JUNRUI, SUN YONGJIE, DU YANKANG
• Format: Patent
• Language: Chinese; English
• Published: 22.02.2012
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

The invention discloses a single-event-upset resistant scan structure D trigger capable of being reset synchronously, and aims to improve the single-event-upset resistance of the single-event-upset resistant scan structure D trigger capable of being reset synchronously. The single-event-upset resistant scan structure D trigger capable of being reset synchronously consists of a clock circuit, a scanning control buffer circuit, a master latch, a slave latch, a first phase inverter circuit and a second phase inverter circuit, wherein the master latch consists of eighteen P-type metal-oxide semiconductor (PMOS) tubes and eighteen N-type metal-oxide semiconductor (NMOS) tubes; the slave latch consists of ten PMOS tubes and ten NMOS tubes; and both the master latch and the slave latch are subjected to duplication redundancy reinforcement, and clocked complementary metal-oxide semiconductor (C MOS) circuit structures in the master latch and the slave latch are improved, namely pull-up circuits and pull-down circuits