Method for fabricating a gate structure

• Main Authors: CHEN KUANUNG, LO HSIENING, TSAI HAN-TING, WANG HAITING, HING FUNG KA, LU WEI-YUAN, CHENG CHUN-FAI
• Format: Patent
• Language: Chinese; English
• Published: 21.09.2011
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to a method for fabricating an integrated circuit, especially relates to a method for fabricating a semiconductor device with a gate structure. A method for fabricating a gate structure, comprises: providing a silicon substrate; depositing an patterning a dummy oxide layer and a dummy gate electrode layer on the substrate; forming a sacrificial layer to surround the dummy oxide layer and the dummy gate electrode layer; forming a nitrogen-containing dielectric layer to surround the sacrificial layer; forming an interlayer dielectric layer to surround the nitrogen-containing dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode. The increased dimensions of the gate structure are wide enough to accommodate the thickness of gate dielectric in the 'high-k last' process, therebymaintaining the device pe