Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution

Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads...

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Bibliographic Details
Main Authors LATORRE FERNANDO, GONZALEZ ANTONIO, LOPEZ PEDRO, MADRILES CARLOS, GIBERT ENRIC, CODINA JOSEP M, MARTINEZ ALEJANDRO, MARTINEZ RAUL
Format Patent
LanguageChinese
English
Published 31.08.2011
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.
Bibliography:Application Number: CN200980139244