Vertical double-diffused MOS transistor testing structure

• Main Authors: LIU XIANZHOU, KE LISI
• Format: Patent
• Language: Chinese; English
• Published: 31.08.2011
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

A vertical double-diffused MOS transistor testing structure belongs to the technical field of semiconductors and comprises a semiconductor substrate, an epitaxial layer, a source doping region, a drain doping region, a channel region, an interlayer dielectric layer, a metal layer which covers the upper surface of the semiconductor substrate and is used for leading out a source electrode and a drain electrode, as well as a back metal layer covering the bottom surface of the semiconductor substrate, wherein the parts of the channel region below the source doping region and the drain doping region are overlapped to form a combined channel; a electrode led out by the metal layer which covers the surface of the epitaxial layer and is used for leading the drain electrode is a drain electrode used for testing, and the electrode led out by the back metal layer covering the bottom surface of the semiconductor substrate is just the true drain electrode of the vertical diffused MOS transistor. By taking the drain electr