Direct memory access controller

A system has a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode, a plurality of system components operable to operate in a sleep or low power mode and in an active mode, and a direct memory access (DMA) controller operating independently from the C...

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Bibliographic Details
Main Authors PESAVENTO RODNEY J, TRIECE JOSEPH W
Format Patent
LanguageChinese
English
Published 21.11.2012
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A system has a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode, a plurality of system components operable to operate in a sleep or low power mode and in an active mode, and a direct memory access (DMA) controller operating independently from the CPU and operable to operate in a sleep or low power mode and in an active mode, wherein the DMA controller is further operable to transfer data from and to a memory or peripheral device, wherein when the system is in a sleep or low power mode, only the DMA controller and any system component which isnecessary to perform a DMA transaction are switched into active mode.
Bibliography:Application Number: CN2007846042