Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

The invention relates to a method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is...

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Bibliographic Details
Main Authors GREELEY JOSEPH, NIROOMAND ARDAVAN, MENG SHUANG, ZHOU BAOSUO
Format Patent
LanguageChinese
English
Published 22.07.2009
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The invention relates to a method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
Bibliography:Application Number: CN200780026005