Noise isolation between circuit blocks in an integrated circuit chip

An integrated circuit (10) includes a p-well block region (30) having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block (22) and a second circuit block (24). The integrated circuit (10) further includes a...

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Bibliographic Details
Main Authors SECAREANU RADU M, BANERJEE SUMAN K, HARTIN OLIN L
Format Patent
LanguageChinese
English
Published 08.12.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An integrated circuit (10) includes a p-well block region (30) having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block (22) and a second circuit block (24). The integrated circuit (10) further includes a guard region (32) formed surrounding the p-well block region (30) for providing noise isolation between the first circuit block (22) and the second circuit block (24).
Bibliography:Application Number: CN2007806446