Bit line contact forming method

• Main Authors: YANG ZHONGHUI, SUN ZHIJIANG, CAI XINYU, CHEN WENLI
• Format: Patent
• Language: Chinese; English
• Published: 26.11.2008
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A bit-line contact forming method includes steps of providing a semiconductor substrate, forming a bit-line implantation area in the semiconductor substrate, forming a medium layer on the semiconductor substrate and forming an opening on the medium layer, forming a plug implantation area on the semiconductor substrate, forming a titanium layer and a titanium nitride layer on the medium layer and the side wall and bottom of the opening, and annealing the plug implantation area and titanium layer simultaneously to form bit-line contact. Because the bit-line contact forming method anneals the formed plug implantation area and the formed titanium layer simultaneously, and annealing can be completed under low temperature, a formed titanium silicide layer has uniform thickness, and can not increase leakage current. Simultaneously, the high-temperature chemical vapor deposition process of the prior art is not utilized to form the titanium silicide layer, thereby reducing thermal budget of semiconductor elements, and