Tiled prefetched and cached depth buffer

A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value comp...

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Bibliographic Details
Main Authors SHIPPEE GEOFFREY, DHAWAN RAJAT RAJINDERKUMAR, ANDERSON MICHAEL HUGH, CHUANG DAN MINGLUN
Format Patent
LanguageChinese
English
Published 07.05.2008
Subjects
CALCULATING
COMPUTING
COUNTING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Summary:A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.
Bibliography:Application Number: CN200680016684