Synchronising a translation lookaside buffer to an extended paging table

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas...

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Bibliographic Details
Main Authors NEIGER GILBERT, UHLIG RICHARD, RUST CAMRON, SCHOENBERG SEBASTIAN, MADUKKARUMUKUMANA RAJESH, RODGERS DION
Format Patent
LanguageChinese
English
Published 26.03.2008
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
Bibliography:Application Number: CN200710142706