Structure and method for forming semiconductor component

• Main Author: YANG HAINING,PORTER R. J.,UTOMO H. K.,WANG YUNYU
• Format: Patent
• Language: English
• Published: 21.11.2007
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The present invention provides a semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSix). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSix) into a second phase (MSiy) with x<y. The metal silicide conversion causes either volumetric shrinkage or expansion in the S/D metal silicide layers of the FET, which in turn generates intrinsic tensile or compressive stress in the S/D metal silicide layers under confinement by the silicon nitride layer.