Memory with charge storage locations

A memory having gate structures adjacent opposing sidewalls of a semiconductor structure (1105) includes a channel region (1725) and a plurality of charge storage locations (1713, 1715, 1709, and 1711) between the gate structures and the opposing sidewalls. The channel region is located between two...

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Bibliographic Details
Main Authors MATTHEW LEO, STEIMLE ROBERT F, MURALIDHAR RAMACHANDRAN
Format Patent
LanguageChinese
English
Published 03.02.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A memory having gate structures adjacent opposing sidewalls of a semiconductor structure (1105) includes a channel region (1725) and a plurality of charge storage locations (1713, 1715, 1709, and 1711) between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell canbe implemented in an array (1801) of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.
Bibliography:Application Number: CN200480014053