Low-density odd-even checking codec hardware simulation system based on programmable gate array

The invention discloses a kind of LDPC encode and decode hardware emulate system basing on FPGA. The system includes the control software of PC terminal and the hardware basing on DPFA which includes the control module of PCI interface, random number generator, Gaussian noise generator, LDPC encoder...

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Bibliographic Details
Main Authors GAO MINGLUN, DONG LAN, LI WEI, LI LI, ZHANG ZHONGJIN, ZHANG CHUAN, HE SHUZHUAN
Format Patent
LanguageChinese
English
Published 18.02.2009
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
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Summary:The invention discloses a kind of LDPC encode and decode hardware emulate system basing on FPGA. The system includes the control software of PC terminal and the hardware basing on DPFA which includes the control module of PCI interface, random number generator, Gaussian noise generator, LDPC encoder/decoder and so on. The invention bases on FPGA hardware and realizes simulation study of the LDPC, at the same time, the system is good at controllability, observation and reusability, and improves the pace of simulation ( is more than 300 times higher than the pace of the simulation software), offering a good lab environment for researching the same kind of error correcting codes further.
Bibliography:Application Number: CN200710132285