INTEGRATED LEVEL DETECTOR CIRCUIT WITH GATING ARRANGEMENT TO INHIBIT TRANSIENT OUTPUT SIGNALS IN RESPONSE TO ENERGIZATION OF THE CIRCUIT

• Main Authors: HEALEY R, PLANY J
• Format: Patent
• Language: English
• Published: 03.04.1973
• Subjects: MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

A level detector circuit suitable for embodiment in integrated circuit form includes a comparator circuit and reference voltage generator energized by a common voltage source. The level detector monitors the voltage of an incoming signal by utilizing the comparator circuit to compare this signal with the generated reference voltage. The reference voltage is generated in response to a current source energizing a breakdown diode. The output of the comparator is temporarily inhibited during the transient initial energization of the comparator and the reference voltage generator to prevent false alarm signals. The output is inhibited by an inhibit gate circuit arrangement which is energized by a driving circuit operative prior to breakdown of the breakdown diode. An additional feature of the invention is a signal inversion scheme energized by the reference voltage generator which permits voltages of opposite polarity to that of the reference and energization voltages to be compared with the magnitude of the reference voltage by the comparator.