MULTI-THREADED TRANSLATION AND TRANSACTION RE-ORDERING FOR MEMORY MANAGEMENT UNITS

Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address...

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Bibliographic Details
Main Authors MOREIRA, CARLOS JAVIER, SOMASUNDARAM, MANOKANTHAN, PODAIMA, JASON EDWARD, GADELRAB, SERAG MONIER, MIRETSKY, ALEXANDER, ERNEWEIN, KYLE JOHN, CHOUDRY, MUHAMMAD UMAR, VARIA, MEGHAL, WIERCIENSKI, PAUL CHRISTOPHER JOHN
Format Patent
LanguageEnglish
French
Published 08.12.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.
Bibliography:Application Number: CA20162983797