INTEGRATED CIRCUIT STACK INCLUDING A PATTERNED ARRAY OF ELECTRICALLY CONDUCTIVE PILLARS

The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically...

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Bibliographic Details
Main Authors TUCKER, JAMES L, VOGT, ERIC E, DOUGAL, GREGOR D
Format Patent
LanguageEnglish
French
Published 10.01.2023
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer. Il est décrit un système de circuits intégrés empilés qui comprend deux couches conductrices intégrées empilées de chaque côté dune couche dinterposition. La couche dinterposition peut comprendre au moins une puce de circuit intégré et une partie dinterposition qui comprend plusieurs piliers conducteurs disposés dans un réseau à motifs latéraux à lintérieur de la couche dinterposition.
Bibliography:Application Number: CA20162926991