FORWARD ERROR CORRECTION (FEC) ON A LINK BETWEEN ICS

An apparatus suitable for generating a signal for transmission over a link between two ICs is provided. The apparatus receives an input signal comprisi ng payload data to be transmitted and processes the payload data in the input signal to derive forward error correction data. An output signal is ge...

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Bibliographic Details
Main Author GAGNON, RONALD J
Format Patent
LanguageEnglish
French
Published 10.10.2002
Edition7
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:An apparatus suitable for generating a signal for transmission over a link between two ICs is provided. The apparatus receives an input signal comprisi ng payload data to be transmitted and processes the payload data in the input signal to derive forward error correction data. An output signal is generate d, the output signal comprising the payload data received in the input signal a nd the generated forward error correction data. The output signal is released f or transmission over the link between two ICs. The link between two ICs may include for example a backplane or a link between two ICs on a same circuit pack. The use of forward error correction data in a signal carried over a conducting medium suitable for carrying electrical signals is also provided.
Bibliography:Application Number: CA20022443084