COLUMN REDUNDANCY CIRCUIT WITH REDUCED SIGNAL PATH DELAY
The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redunda...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English French |
Published |
29.07.2008
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!