COLUMN REDUNDANCY CIRCUIT WITH REDUCED SIGNAL PATH DELAY
The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redunda...
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Main Authors | , , |
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Format | Patent |
Language | English French |
Published |
29.07.2008
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Subjects | |
Online Access | Get full text |
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Summary: | The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redundant column drivers distributed throughout memory banks and flexibly selectable to replace faulty columns within multiple blocks within a bank; and switch means for selectively activating the redundant column and preventing the activation of a defective normal column, whereby the column redundancy method and apparatus minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required to be blown in repairing faulty columns addresses. |
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Bibliography: | Application Number: CA19992347765 |