AUTOMATED VALIDATION AND VERIFICATION OF COMPUTER SOFTWARE

A method and apparatus for automating validation and verification of computer software confirms that during a test execution of the software, all lines of code are executed and all branches in the software are taken or not taken at least once. The computer software to be tested is compiled and a lin...

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Bibliographic Details
Main Authors GOOSSEN, EMRAY R, SHEMA, DAVID K, LIPPITT, CARL E
Format Patent
LanguageEnglish
French
Published 08.04.1999
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method and apparatus for automating validation and verification of computer software confirms that during a test execution of the software, all lines of code are executed and all branches in the software are taken or not taken at least once. The computer software to be tested is compiled and a link map is generated. After compilation of the code, it is run in a test fixture to test all the design functions. During this test execution, a monitoring process is performed which documents which lines of code have been executed and when and when not certain branches were taken. Two maps are generated which indicate what instruction branches were taken and were not taken. A comparison is then made between the link map originally generated and the two branch maps generated to determine what lines of code were executed, whether each branch was taken at least once, and whether a branch was not taken.
Bibliography:Application Number: CA19982304314