INTERNAL CACHE MICROPROCESSOR SLOWDOWN CIRCUIT WITH MINIMAL SYSTEM LATENCY

A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with applications software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to...

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Bibliographic Details
Main Authors THOMA, ROY E., III, HAMID, MUSTAFA A, THAYER, JOHN S
Format Patent
LanguageEnglish
French
Published 04.05.1991
Edition5
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with applications software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the. processor in a halted state.
Bibliography:Application Number: CA19902025439