SERIAL CHIP SCAN

Disclosed is a scan apparatus which provides an interface and control signals between a secondary computer and data locations in a host computer. The scan apparatus functions independently of the normal operation of the host computer. Scan-out is performed transparently to the operation of the host...

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Bibliographic Details
Main Authors SHACKLEFORD, JAMES B, SI, STEPHEN S.C, ALLRED, DARYL H
Format Patent
LanguageEnglish
French
Published 17.02.1987
Edition4
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:Disclosed is a scan apparatus which provides an interface and control signals between a secondary computer and data locations in a host computer. The scan apparatus functions independently of the normal operation of the host computer. Scan-out is performed transparently to the operation of the host computer. The host computer is constructed using circuits on semiconductor chips. The semiconductor chips are organized in blocks. Chips within each block include scan apparatus which controls the scan operations in connection with that chip. The scan apparatus in each chip is connected through two I/O pins to a clock lines and to a bidirectional scan data line. The scan apparatus on each chip includes a multimedia sequencer so that each chip in each block can be independently performing scan sequences. The block scan apparatus and the secondary computer perform the functions of requesting a scan sequence for transmitting the scan data.
Bibliography:Application Number: CA19840461856