CURRENT WEIGHTING CIRCUIT

PHF. 79-539 Div. 28 A circuit for weighting a plurality of input currents and for forming their sum comprises a first transistor, whose emitter is coupled to a power supply terminal via two series-connected first resistors, one end of each resistor being connected to an input terminal, whose collect...

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Bibliographic Details
Main Author FERRIEU, GILBERT M.M
Format Patent
LanguageEnglish
French
Published 25.10.1983
Edition3
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TELEPHONIC COMMUNICATION
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Summary:PHF. 79-539 Div. 28 A circuit for weighting a plurality of input currents and for forming their sum comprises a first transistor, whose emitter is coupled to a power supply terminal via two series-connected first resistors, one end of each resistor being connected to an input terminal, whose collector is energized by a current source and whose base is connected to a current source and to a diode which is connected to the emitter of a composite second transistor, whose emitter is connected to the power supply terminal via a second resistor and whose collector is connected to the output terminal, the weighting coefficients of the input currents each being determined by the ratio between the value (r or r+p) of the first resistors present between an input terminal and the power supply terminal and the value (q) of the second resistor. Such circuits are suitable for use in a subscriber telephone line interface circuit in which the weighted sum is to be formed of the currents entering and leaving the subscriber's line with a precise adjustment of the weighting coefficients.
Bibliography:Application Number: CA19810372904