DISPOSITIVO PARA PAGINACAO DE MEMORIO NUM MICROCOMPUTADOR

In a microcomputer system having a main memory accessed by both a central processor unit (20) and a CRT controller (21), a page register system (30) receives page bits defining both CPU and CRT pages from CPU. The CPU page bits are combined with lower order address bits from CPU for CPU access cycle...

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Bibliographic Details
Main Author DAVID ALLEN KUMMER
Format Patent
LanguagePortuguese
Published 09.07.1985
Edition4
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In a microcomputer system having a main memory accessed by both a central processor unit (20) and a CRT controller (21), a page register system (30) receives page bits defining both CPU and CRT pages from CPU. The CPU page bits are combined with lower order address bits from CPU for CPU access cycles, and CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both CPU and CRT controller can access any of pages in memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside range of addresses for memory. When a decoder (42) detects such addresses, it directs CPU address bits, corresponding in order to CPU page bits issued by the register system, to address memory.
Bibliography:Application Number: BR19848403981