PROCEDE ET APPAREIL POUR EXECUTER UN OPERATEUR DE STOCKAGE DANSUNE UNITE DE TRAITEMENT DE DONNEES

• Main Authors: B.A. DENT, E.A. HAUCK, B.A. CREECH
• Format: Patent
• Language: French
• Published: 31.12.1970
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

1,268,984. Digital computers. BURROUGHS CORP. 13 May, 1970 [30 July, 1969], No. 23123/70. Headings G4A and G4C. A digital data processor includes a memory containing operand words and address reference words, an operand word being located directly through a first address reference word or indirectly through said latter word and further word(s) referenced thereby, whereby the processor can scan through the memory until an operand is found, and then another operand can be stored in its location. A store operator in store 24 controls a cycling circuit 36 and also determines whether the former operand is erased or stored elsewhere. There are four types of address reference word (Fig. 3, not shown) and together with the operand word they include parts identifying their type &c. Operation (Figs. 2A to 2E, not shown).-Initially an operator has been read out of the core memory 38 and stored in operator register 24. The A register 12 contains a first operand to be stored in the core memory in response to the store operator in register 24, and the B register 14 contains one of the address reference words. Firstly the contents of registers A and B are interchanged and then (or if the content were that way initially) the address word goes from the A register to the C register 10. A decoder 26 determines whether the address word is IRW or IRWS, and a separate routine is entered (see below). If it is neither, the decoder then checks if it is a DD failing which an invalid condition exists and the operation is interrupted. DD flow (Fig. 2B).-Initially the P bit of the DD address is checked to ensure that the oper- and referenced by the DD is present; if not, an error exists and an interrupt is made. If it is, the length and address parts of the DD are added together in binary full adder 20 to form the absolute address which is stored in MM register 22. A memory cycle (see below) is then initiated and a fresh word transferred to the C register 10. The new operand word in C register 10 is checked to see if it is a DD and if so, the cycle is repeated. If not, depending on whether the store operator is destructive or non- destructive, the first operand in the B register is erased or retained. Memory cycle (Fig. 2E).-The first operand in the B register is transferred into register 48 in the memory and sets a memory counter 60 into state 1 and the address is transferred to register 40. During state 2, the read/write unit 44 causes the content of the memory location specified by the word of the address in register 40 to be transferred to register 46. If bit 49 in the content word is a 1, it indicates that the word is a non-operand non-erasable word and the word is restored in the core in its original position. If bit 49 is a 0, the word is an operand and hence the first operand in register 48 is stored in the location from which the word in register 46 is read, and the latter word goes to register 10. IRW or IRWS flow (Fig. 2C).-The IRW or IRWS is stored in both A and C registers and the A register is then checked to see if it is an IRW or an IRWS. If it is an IRW, an absolute address is formed (from the C register using adder 20) which points to a word within the same address stack. An IRWS points to a word outside the same address stack. In either case a word is selected using the memory cycle as before and, if the word is not an operand, the non-operand address reference word is copied into register C and the cycle repeated until an operand is located into whose location the first operand can be stored. (Fig. 2D, terminal flow). During terminal flow any PCW word is considered. Other features.-The memory is made of cores and the registers are of flip-flops.