A single step electroplating process for interconnect via fill and metal line patterning

A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a...

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Bibliographic Details
Main Authors KEVIN J. LEE, SAM SIVAKUMAR, MAKAREM HUSSEIN
Format Patent
LanguageEnglish
Published 19.07.1999
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.
Bibliography:Application Number: AU1616699