AUFRECHTERHALTUNG DER CACHESPEICHERKOHERENZ ZUM DIREKTEN ZUGRIFF (DMA), ABSCHLUSS EINER AUFGABE, ZUR SYNCHRONISIERUNG

A memory cache control arrangement for performing a coherency operation on a memory cache (105) comprises a receive processor for receiving (301) an address group indication for an address group comprising a plurality of addresses associated with a main memory (103). The address group indication may...

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Bibliographic Details
Main Authors EFRAT (YACOV), JACOB, PELED, ITAY, ANSCHEL, MOSHE, ELDAR, ALON
Format Patent
LanguageGerman
Published 15.03.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A memory cache control arrangement for performing a coherency operation on a memory cache (105) comprises a receive processor for receiving (301) an address group indication for an address group comprising a plurality of addresses associated with a main memory (103). The address group indication may indicate a task identity and an address range corresponding to a memory block of the main memory (103). A control unit 303 processes each line of a group of cache lines sequentially. Specifically it is determined if each cache line is associated with an address of the address group by evaluating a match criterion. If the match criterion is met, a coherency operation is performed on the cache line. The invention allows a reduced duration of a cache coherency operation. The duration is further independent of the size of the main memory address space covered by the coherency operation.
Bibliography:Application Number: AT20040013507T