BEFEHLSPUFFERSYSTEM FÜR EINEN DIGITALEN RECHNER

An instruction buffer for a digital computer controls the flow of instruction stream to an instruction decoder (32). As each instruction is consumed, a shifter (70) removes the consumed bytes and repositions the remaining bytes into the lowest order positioned. The byte positions left empty are fill...

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Bibliographic Details
Main Authors MURRAY, JOHN E, MCKEON, MICHAEL M, MANLEY, DWIGHT P, HETHERINGTON, RICKY C, FITE, DAVID B
Format Patent
LanguageGerman
Published 15.08.1997
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An instruction buffer for a digital computer controls the flow of instruction stream to an instruction decoder (32). As each instruction is consumed, a shifter (70) removes the consumed bytes and repositions the remaining bytes into the lowest order positioned. The byte positions left empty are filled by instruction stream bytes retrieved from one of a pair of prefetch buffers (64, 66) or from a virtual instruction cache (28). One prefetch buffer (66) is filled from the instrction cache (28) after being emptied, but prior to those particular bytes being requested to fill the instruction decoder (32). The two-level prefetching allows the relatively slow process of cache access to be performed during noncritical time.
Bibliography:Application Number: AT19890309274T