A 10-bit 50MS/s SAR ADC in 65nm CMOS with on-chip reference voltage buffer

• Published in: Integration (Amsterdam) Vol. 50; pp. 28 - 38
• Main Authors: Harikumar, Prakash, Wikner, J. Jacob
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.06.2015
• Subjects: Bootstrapped switches; On-chip reference voltage buffer; SAR ADC; On-chip reference voltage buffer; SAR ADC; Bootstrapped switches
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2015.01.002

This paper presents the design of a 10-bit, 50MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25bits at a supply voltage of 1.2V, typical process corner and sampling frequency of 50MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697μW and achieves an energy efficiency of 25fJ/conversion-step while occupying a core area of 0.055mm2. •The limitation posed by incomplete DAC settling in medium-to-high speed SAR ADCs is addressed.•The design details of a high-speed reference voltage buffer (RVBuffer) are elaborated.•Estimation of key performance parameters of the RV Buffer are provided.•Post-layout simulation of the full ADC including device noise and IO pad parasitics has been reported.