A 0.35V, 375kHz, 5.43µW, 40nm, 128kb, symmetrical 10T subthreshold SRAM with tri-state bit-line

• Published in: Microelectronics Vol. 51; pp. 89 - 98
• Main Authors: Wu, Shang-Lin, Lu, Chien-Yu, Tu, Ming-Hsien, Huang, Huan-Shun, Lee, Kuen-Di, Kao, Yung-Shin, Chuang, Ching-Te
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.05.2016
• Subjects: 10T cell; Low power; Subthreshold SRAM; Write-assist; 10T cell; Subthreshold SRAM; Low power; Write-assist
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2016.02.011

This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tri-state pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128kb SRAM macro implemented in 40nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with VDD down to 0.35V (~100mV lower than the threshold voltage). Data is held down to 0.325V with 2.53µW standby power. The measured maximum operation frequency is 375kHz with total power consumption 5.43µW at 0.35V.