3 - Underneath the Hood of the dsPIC DSC
Digital signal controller (DSC) is a new class of processor that couples the powerful mathematical processing performance of a pure digital signal processor with the highly deterministic behavior of standard microcontrollers. One such DSC is the dsPIC® DSC microcontroller from Microchip that integra...
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Published in | Intelligent Sensor Design Using the Microchip dsPIC pp. 53 - 98 |
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Main Author | |
Format | Book Chapter |
Language | English |
Published |
Elsevier Inc
2006
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Online Access | Get full text |
ISBN | 0750677554 9780750677554 |
DOI | 10.1016/B978-075067755-4/50006-7 |
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Summary: | Digital signal controller (DSC) is a new class of processor that couples the powerful mathematical processing performance of a pure digital signal processor with the highly deterministic behavior of standard microcontrollers. One such DSC is the dsPIC® DSC microcontroller from Microchip that integrates a tremendous amount of functionality into a single chip, allowing designers to create robust sensing and control solutions in a very small package. The three useful perspectives of the dsPIC DSC include an examination of the chip's data-processing architecture, a study of the mathematical representations and operations that the chip supports, and an analysis of the various on-chip peripheral components. A thorough understanding of these three subjects will serve as a solid foundation for creating meaningful systems using the chip. The dsPIC family of products is designed specifically for the high-speed processing of mathematically intensive operations, with dedicated hardware elements that handle time-intensive processes with minimal loading of the core processor. An understanding of the dsPIC DSC begins with its memory architecture, because it is one of those elements specifically designed to address the data-throughput requirements of a digital signal processing system. The dsPIC DSC employs a modified Harvard architecture that has a separate program memory and data memory busses, allowing the processor to simultaneously fetch both an instruction and the data upon which that instruction will operate. |
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ISBN: | 0750677554 9780750677554 |
DOI: | 10.1016/B978-075067755-4/50006-7 |