Improved three-phase dynamic current mode logic-based D flip-flop design against power attacks(基于DyCML的改进型三阶段抗功耗攻击型D触发器)

• Published in: Zhejiang da xue xue bao. Journal of Zhejiang University. Sciences edition. Li xue ban Vol. 52; no. 4; pp. 424 - 430
• Main Authors: 姚茂群(YAO Maoqun), 李聪辉(LI Conghui), 李海威(LI Haiwei), 陈冉(CHEN Ran)
• Format: Journal Article
• Language: Chinese
• Published: Zhejiang University Press 01.07.2025
• ISSN: 1008-9497
• DOI: 10.3785/j.issn.1008-9497.2025.04.002

Differential Power Attack (DPA) brings a significant security challenge for hardware, as it involves the examination of power consumption data from circuits to extract sensitive information. The security performance of a circuit is intrinsically linked to the resilience of its flip-flop components against power attacks. This paper presents a novel design for a D flip-flop that is resistant to power consumption attacks, utilizing the DyCML structure. The proposed design incorporates a three-phase logic to avoid security vulnerabilities arising from unbalanced load capacitance within the circuit. Furthermore, the three-phase logic is enhanced by employing internal node signals to generate the discharge signal, thereby preventing potential attackers from compromising the discharge signal's integrity by manipulating the clock frequency, which could undermine the circuit's resistance to power consumption attacks. Through Hspice simulations, with two introduced parameters, i.e., normalized energy deviation (NED) an