Two Methods for Linearity Improvement in Digitally Controlled Delay Elements: Current Starved Type

Current starved delay elements (CSDEs) are among the popular architectures to manipulate rising or falling edges of signals in order to meet timing requirements. The digitally controllable generations of these topologies are now monotonic and reasonably power efficient, but they lack linearity in fu...

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Bibliographic Details
Published inMajlesi Journal of Electrical Engineering (Print) Vol. 11; no. 1
Main Authors Ali Nehbandan Dokht, Mahmoud Ghasemi, Abbas Golmakani
Format Journal Article
LanguageEnglish
Published OICC Press 01.02.2024
Subjects
Current starved
Delay Element
Linearity
Monotonic
Power
Process
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ISSN2345-377X
2345-3796

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Summary:Current starved delay elements (CSDEs) are among the popular architectures to manipulate rising or falling edges of signals in order to meet timing requirements. The digitally controllable generations of these topologies are now monotonic and reasonably power efficient, but they lack linearity in full range. Inherently, this subject may not seem problematic because by setting the dimensions of the design elements the desired delay can be acquired. However, in case that a chain of incremental delays are required we tend to employ more linear designs. In this paper two improvements in linearity are examined for two known CS designs. Both of the topologies are in 0.18um technology and meet appropriate design parameters like power, area and monotonic response.
ISSN:2345-377X
2345-3796