Design of a Floating-bulk NMOS Triggered GGNMOS with Low Triggering Voltage and High Robustness Aimed at 3.3 V I/O ESD Protectio

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Bibliographic Details
Published in	Journal of semiconductor technology and science Vol. 25; no. 3; pp. 218 - 227
Main Authors	Chen, Haotian, Wang, Yang, Yang, Hongjiao, Ding, Liqiang, Liu, Wei, Deng, Jun, Zhou, Fengfeng, Nie, Beibei
Format	Journal Article
Language	English
Published	30.06.2025
Online Access	Get full text

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ISSN:	1598-1657 2233-4866
DOI:	10.5573/JSTS.2025.25.3.218