Advantageous Sampling of Correlated Current Signals to Supress Fixed-Pattern Noise in CMOS Imagers

• Published in: Journal of Integrated Circuits and Systems Vol. 12; no. 1; pp. 47 - 55
• Main Authors: Souza, R. A., Ventura, L. G. M., Martins, A. R. S., Monteiro, D. W. de Lima, Salles, L. P.
• Format: Journal Article
• Language: English
• Published: 28.12.2020
• ISSN: 1807-1953; 1872-0234
• DOI: 10.29292/jics.v12i1.450

The Active Pixel Sensor (APS) has been a vastly used integrated circuit topology in CMOS imagers. Mismatch of physical parameters among pixels, caused by process variations, introduces Fixed-Pattern Noise (FPN) at the array output. Correlated Double Sampling (CDS) in voltage mode is a commonly used method to suppress the offset caused FPN. However, it increases the complexity as well as the demanded silicon area of either the pixel or the external circuitry, besides having its signal swing restricted by the supply voltage. An alternative CDS circuit operating in current mode to reduce FPN is presented in this paper. The correlated current signals are sampled and subtracted using a simpler circuitry, leading to a more efficient relation of FPN reduction for the required silicon area. Furthermore, this technique does not change the APS topology or basic operation cycle. A simulated and tested CDS alternative is presented, and a simulated further improved version is proposed. Simulation and experiments showed a 40% FPN reduction with the fabricated CDS, whereas the improved simulated version ensures 90% FPN reduction.